QONTOS-1 is the first-machine assembly of the QONTOS architecture. One thousand superconducting transmons across two cryostat-mounted modules are joined by a heralded electro-optic interconnect at 1,550 nm. Programme acceptance is gated by four engineering milestones: architecture freeze at G1, module acceptance at G2, Bell-pair validation at G3, and the first logical qubit at G4.
The first-machine programme retires architectural risk one acceptance gate at a time.
QONTOS-1 is not specified to deliver fault-tolerant computation. It is specified to retire, at a measurable subsystem gate, every architectural risk that stands between the present superconducting platform and a fault-tolerant successor: chiplet IO, control-density on the mixing chamber, microwave-to-optical transduction efficiency, decoder latency, and cross-module Bell-pair fidelity.
The runtime is operational against simulator and external-provider backends today. At G2, the same compiled plan switches over to QONTOS-1 hardware through a single ExecutorContract. Plan-time work is identical; only the executor changes.
DOWNLOAD WHITEPAPER · V5.4 ↗The first-machine specification is a strict subset of the QONTOS family arc. Every subsystem that ships in QONTOS-1 either becomes a building block of QONTOS-2 or sets the engineering constraint that the successor generation is sized to outperform. Five subsystems carry the assembly; four engineering gates measure it; one runtime addresses every backend the programme can target.
Two independent dilution refrigerators, five tantalum-on-silicon transmon chiplets per module, heavy-hex intra-chiplet topology with tunable-coupler CZ gates.
Microwave-to-1,550 nm transduction through a LiNbO₃ resonator at the 100 mK still plate. Cooperativity C = 1 sets the impedance-matched conversion point.
FPGA sequencer closes the stabilizer round in 1 μs; the MWPM decoder farm matches the syndrome in 5 μs; feed-forward correction emerges within 10 μs total.
The QONTOS runtime addresses simulator, IBM Quantum, Amazon Braket, and the native QONTOS-1 executor through a single ExecutorContract. Compile once, route anywhere.
Every run emits a cryptographic proof chain binding circuit, plan, and result. The artefact replays the run end to end; tampering at any stage invalidates it.
Each generation is sized against the engineering risk retired by the one before it. QONTOS-1 specifies two modules and one logical qubit; QONTOS-2 quadruples the module count; QONTOS-3 carries the architecture into the commercial fault-tolerant regime. Targets are engineering objectives gated by subsystem milestones, not measured performance.
QONTOS-1 acceptance is the moment the architecture is proved. The QONTOS-2 programme begins at G4, not before; gates are acceptance criteria rather than calendar promises. Organisations on the specification register receive subsystem updates as gates retire.
Request the specificationFive-stage dilution refrigerator: 295 K / 50 K / 4 K / 100 mK still / ≤ 20 mK mixing chamber. The mixing chamber holds the qubit chip and the readout resonators. Cooling power target ≥ 25 μW at 20 mK; passive load below 1 μW from wiring.
Five tantalum-on-silicon transmon chiplets, 100 qubits each. Heavy-hex topology intra-chiplet, through-silicon superconducting routing chiplet-to-chiplet. Tunable-coupler CZ gates with 5×10⁻³ target error.
Staged at the 100 mK still plate. Up-converts a microwave photon at 5 GHz to a telecom-band photon at 1,550 nm. Cooperativity C = 1 sets the impedance-matched conversion point; η ≥ 0.1 % is the QONTOS-1 base acceptance target and η ≥ 1 % remains a research threshold.
50/50 beam splitter and SNSPDs sit on the 1.5 K stage outside the cryostat. A coincidence click is forwarded to the FPGA sequencer within five microseconds. Only heralded rounds count as Bell pairs.
Room-temperature rack: AWGs at 1 ns resolution, FPGA stabilizer sequencer, digitiser, MWPM decoder farm, and the QONTOS runtime host. Total feed-forward correction time ≤ 10 μs.
Each QONTOS-1 module integrates two device classes on the mixing-chamber plate. Five data chiplets carry one hundred tantalum-on-silicon transmons each in a heavy-hex tunable-coupler lattice. A paired characterisation chip carries five frequency-fixed transmons for per-qubit calibration, pulse-shape R&D, and decoherence characterisation under the same readout chain.
The QONTOS-1 deliverable is a complete two-module assembly bound to the runtime, not a bare qubit device:
The assembly is qualified against a commercial dilution-refrigerator envelope meeting:
The runtime accepts circuits today against simulator and external-provider backends. Native execution joins at G2.
Organisations placed on the specification register receive the full QONTOS-1 engineering specification, dispatches as each acceptance gate retires, and supply-chain briefings ahead of public release. The register is closed; correspondence is not redistributed.
The first-machine assembly opens three categories of investigation for the quantum-engineering community: distributed fault-tolerant operation at the smallest physically meaningful module count, compiler and runtime research against a real distributed backend, and microwave-to-optical transduction physics at full system scale.
The first-machine assembly executes a distance-d surface-code logical qubit across the module boundary. Lattice-surgery merges between the two patches are mediated by heralded Bell pairs delivered through the interconnect; the seam closes after d code cycles to realise an effective transversal CNOT.
Distributed logical-memory experiments. Inter-module lattice-surgery characterisation. Distance-scaling studies preparing the QONTOS-2 logical envelope. Multi-patch error budget allocation.
The QONTOS runtime is plan-time identical across every backend it addresses. The partitioner, scheduler, decoder pipeline, and proof chain that will drive native execution at G2 are the same artefacts that drive simulator and external-provider execution today.
Partitioner optimisation against real distributed targets. Decoder benchmarking against measured syndrome distributions. Proof-chain audit tooling. Verifiable replay of historical runs across heterogeneous executors.
The first-machine assembly hosts the transducer subsystem at full system scale. QONTOS-1 accepts η ≥ 0.1 % as the base target, tracks η ≥ 0.5 % as an aggressive scenario, and treats η ≥ 1 % plus purification overhead as a research threshold for later architecture studies.
Cooperativity scaling beyond C = 1. Pump-loss mitigation under cryogenic constraint. SNSPD bandwidth and dead-time. Phase-lock stability over the 5 m fibre run. Alternative transducer geometries benchmarked against the electro-optic baseline.
The QONTOS-1 assembly is a system-level integration of five subsystem categories: cryogenics, photonics, control electronics, software, and quantum error correction. Each category is qualified against the engineering envelope of the relevant subsystem. Final supplier selections are committed at G1, the architecture-freeze gate.
Dilution refrigerators meeting the ≥ 290 mm mixing-chamber and ≥ 25 μW at 20 mK envelope.
Microwave-to-optical transducer, SNSPD, fibre infrastructure, and 1.5 K staging.
AWG, digitiser, FPGA sequencer, and decoder farm hardware.
Application frameworks, compilers, and execution platforms that target the QONTOS ExecutorContract.
Real-time decoder pipelines, ASICs, and surface-code research collaborators.
The full QONTOS architecture whitepaper, including the QONTOS-1 specification, the photonic interconnect protocol, and the five-generation arc, is now available for external review.
The QONTOS runtime, including the spectral partitioner, MWPM decoder, and three-layer SHA-256 proof chain, is operational against multiple external backends and ready for native-executor binding at G2.
The QONTOS-1 photonic transducer is committed to the electro-optic LiNbO₃ resonator path with piezo-optomechanical kept on the R&D track for later research regimes.
The QONTOS programme develops modular superconducting-photonic quantum computers across a five-generation arc. QONTOS-1 is the first-machine assembly that proves the architecture. QONTOS-2 and QONTOS-3 are conditional scenarios; QONTOS-4 and QONTOS-5 remain research-vision architecture studies.
Each generation is sized against the engineering risk retired by the one before it. The first commercially relevant logical-qubit count is the responsibility of QONTOS-2; full fault tolerance is the responsibility of the three generations that follow.
The QONTOS programme